Microprocessors Suppose you have a perfect clock signal with

Microprocessors

Suppose you have a perfect clock signal with a frequency of 50 MHz. Write a VHDL code that generates a periodic signal with a period of 40.96 micro seconds. In that period of time, the signal stays high only for 320 nano seconds and stays low in the rest of the period.

Solution

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS

COMPONENT test
PORT(clk : IN std_logic;)
END COMPONENT;

signal clk : std_logic := \'0\';
constant clk_periodon : time := 320 ns;
constant clk_periodoff : time := 40960 ns;

BEGIN

uut: test PORT MAP (clk => clk);   

-- Clock process definitions
clk_process :process
begin
clk <= \'0\';
wait for clk_periodoff; --for 4960 ns signal is \'0\'.
clk <= \'1\';
wait for clk_periodon; --for next 320 ns signal is \'1\'.
end process;

END;