In a sidescrolling video game a character moves through an e

In a side-scrolling video game, a character moves through an environment from, say, left-to-right, while encountering obstacles, attackers, and prizes. The goal is to avoid or destroy the obstacles, defeat or avoid the attackers, and collect as many prizes as possible while moving from a starting position to an ending position. We can model such a game with a graph, G, where each vertex is a game position, given as an (x; y) point in the plane, and two such vertices, v and w, are connected by an edge, given as a straight line segment, if there is a single movement that connects v and w. Furthermore, we can dene the cost, c(e), of an edge to be a combination of the time, health points, prizes, etc., that it costs our character to move along the edge e (where earning a prize on this edge would be modeled as a negative term in this cost). A path, P, in G is monotone if traversing P involves a continuous sequence of left-to-right movements, with no right-to-left moves. Thus, we can model an optimal solution to such a side-scrolling computer game in terms of nding a minimum-cost monotone path in the graph, G, that represents this game. Describe and analyze an ecient algorithm for nding a minimum-cost monotone path in such a graph.

Solution

one of the maximum common implementations of the successive approximation ADC, the fee-redistribution successive approximation ADC, makes use of a price scaling DAC. The fee scaling DAC surely includes an array of personally switched binary-weighted capacitors. the amount of fee upon each capacitor within the array is used to perform the aforementioned binary seek at the side of a comparator inner to the DAC and the successive approximation sign in.

First, the capacitor array is absolutely discharged to the offset voltage of the comparator, VOS. This step presents automated offset cancellation(i.e. The offset voltage represents not anything however dead rate which can not be juggled by means of the capacitors).
next, all the capacitors inside the array are switched to the enter signal, vIN. The capacitors now have a fee identical to their respective capacitance times the enter voltage minus the offset voltage upon each of them.
inside the 0.33 step, the capacitors are then switched so that this fee is applied throughout the comparator\'s input, creating a comparator input voltage identical to vIN.
in the end, the actual conversion system proceeds. First, the MSB capacitor is switched to VREF, which corresponds to the entire-scale variety of the ADC. due to the binary-weighting of the array the MSB capacitor forms a 1:1 fee divider with the rest of the array. thus, the input voltage to the comparator is now vIN plus VREF/2. eventually, if vIN is greater than VREF/2 then the comparator outputs a digital 1 because the MSB, otherwise it outputs a digital 0 because the MSB. each capacitor is tested within the equal way until the comparator enter voltage converges to the offset voltage, or at least as near as feasible given the decision of the DAC.