1 What are the digital design entry methods Form your opinio

1) What are the digital design entry methods? Form your opinion, which one is the most efficient? Why?

2) What is the difference between a functional simulation and a timing simulation? Is a functional simulation sufficient enough to ensure the correctness of the design?

Solution

There are following data entry methods:
1 Schematic capture
2 Hardware Description Language (HDL) capture (VHDL, Verilog)

Schematic capture :
Schematic capture is a step in the designing of electronic design automation (EDA) at which the electronic diagram of the electronic circuit is created by a designer. This is done with the help of a schematic capture tool also known as schematic editor.

The circuit design is the very first step of actual design of an electronic circuit. It involves drawing sketches on paper, and then entered into a computer using a schematic editor.

Hardware Description Language (HDL) capture (VHDL, Verilog) :

a. Hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits.
b. It enables a precise, formal description of an electronic circuit that allows for the automated analysis and simulation of an electronic circuit.
c. There are currently two main Hardware Descriptive Languages, VHDL and Verilog.
d. Verilog syntax is not as complicated as VHDL and is less verbose. It lacks features and capabilities that VHDL can provide.
e. Verilog is easier to grasp and understand and its constructs are based on 50% C programming and 50% ADA.
  
Which approach should be used :
a. The hardware description language (HDL) is used at the industry level.
b. HDL allows the designer to organize and integrate complex functions and verify the individual blocks and eventually the entire design with tools like HDL simulators.
c. Schematic capture was a typical design approach was used before but when the average gate count passed the 10,000 gate threshold, they started to break down.

Functional simulators and Timing simulators :
a. Functional simulators verify the logical behavior of a design based on design entry.
b. Timing simulators perform timing verifications at multiple stages of the design. In this simulation the real behavior of the system is verified when encountering the circuit delays and circuit elements in actual device.

As Functional Simulation simply tests the logic \"functional\" operation of the circuit. There is no consideration for delay through the internal logic, We should also use Timing simulation to ensure the correctness of the design.
With Timing Simulation, the delay asociated with the logic elements and the interconnect routing are taken into consideration.