A processor is connected to the memory by an architecture co

A processor is connected to the memory by an architecture composed of an L0 and an L1 cache. The access time of the L0 cache is 1 cycle, for the L1 cache it is 15 cycles, while for the memory 140 cycles. The local miss rate is 9% for the L0 cache and 2% for the L1 cache. a. Compute the average memory access time (AMAT) of the processor. b. What would be the AMAT if the L1 cache would not be present? How much does the L1 cache improve on the memory access time?

Solution

Average memory access time(AMAT) = Hit time L0 + Miss rateL0 × Miss penalty L1

Miss penalty L1 = Hit time L1 + Miss rateL1 × Miss penalty of next memory hierarchy

as there are no more caches

Miss penalty of next memory hierarchy = hit time of main memory.

AMAT = Hit time L0 + Miss rateL0 × (Hit time L1 + Miss rateL1 × hit time of main memory)

=1+0.09*(15+0.02*140)

=2.602 cycles

if the l1 is not present.

  AMAT = Hit time L0 + Miss rateL0 × (hit time of main memory)

1+0.09*140

1+12.6

=13.6

so l1 decreases of 13.6-2.602 = 11 cycles nearly.