The following code is taken from a VHDL file implementing a

The following code is taken from a VHDL file implementing a sequential circuit using two processes (Second process is omitted). The sequential circuit has two inputs (X and clk) and one output (Z). ) Write down the state table implemented by the following VHDL code.

process(State,X) --Combinational Part

begin

case State is

when 0 =>

if X=\'0\' then Z<=\'1\'; Nextstate<=1;

else Z<=\'0\'; Nextstate<=2; end if;

when 1 =>

if X=\'0\' then Z<=\'1\'; Nextstate<=3;

else Z<=\'0\'; Nextstate<=4; end if;

when 2 =>

if X=\'0\' then Z<=\'0\'; Nextstate<=4;

else Z<=\'1\'; Nextstate<=4; end if;

when 3 =>

if X=\'0\' then Z<=\'0\'; Nextstate<=5;

else Z<=\'1\'; Nextstate<=5; end if;

when 4 =>

if X=\'0\' then Z<=\'1\'; Nextstate<=5;

else Z<=\'0\'; Nextstate<=6; end if;

when 5 =>

if X=\'0\' then Z<=\'0\'; Nextstate<=0;

else Z<=\'1\'; Nextstate<=0; end if;

when 6 =>

Z<=\'1\'; Nextstate<=0;

end case;

end process;

Solution

State table: