Digital Logic with Verilog design Here is another state diag

Here is another state diagram: Does this system represent a Moore or Mealy machine? What is the minimum number of flip-flops necessary to represent the required number of states? Define state assignments for each state. How much more work would be required to find and minimize all of the required excitation equations and output logic? How could you use a behavioral description in Verilog to create a module that implements this state machine without doing all of the work identified in d?

Solution

a) This system represents a Mealy machine

b) 6 states would require atleast 3 flipflops log(number of states)

c)

d) First we need to decide which flip flop to be used for implementation. Number of flip flops and work load depends on the type of flipflip being chosen.

State Name	State Number
A	000
B	001
C	011
D	010
E	110
F	110