Based on the following schematic with 3 D flipflops Write co

Based on the following schematic with 3 D flip-flops, Write complete VHDL codes with clock as input, and A, B, C are outputs

Solution

entity count is
Port ( Clock : in STD_LOGIC;
A,B,C : inout STD_LOGIC);
end count;

architecture Behavioral of count is
component DFF
Port ( Clock : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal DA,DB,DC:STD_LOGIC;
begin
DA<=(A xor \'1\');
DB<=(A xor B);
DC<=(A and B)xor C;
uA: DFF(Clock,DA,A);
uB: DFF(Clock,DB,B);
uC: DFF(Clock,DC,C);
end Behavioral;

//code for D Fliflop

entity DFF is
Port ( Clock : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF;

architecture Behavioral of DFF is
begin
process(clk,D)
begin
if(rising_edge(clk)) then
Q <= D;
end if;
end process;
end Behavioral;