this is verilog HDL class Declare the following variables in

this is verilog HDL class

Declare the following variables in Verilog:

a)An 8-bit vector net called a_in.

b)A 32-bit storage register called address. Bit 31 must be the most significant bit. Set the value of the register to a 32-bit decimal number equal to 3.

c)An integer called count.

d)A time variable called snap_shot.

e)An array called delays. Array contains 20 elements of the type integer.

f)A memory MEM containing 256 words of 64 bits each.

g)A parameter cache_size equal to 512.

Solution

a) wire [7:0] a_in; 8 bit vector means requires 0 to 7

b) reg [31:0] address=32’d3;

c) integer cout;

d) time snap_shot;

e) integer delays [0:19];

f) reg [63:0] MEM [0:255];

g) parameter cache_size=512;