Instruction Work in groups of two or three DUE DATE uesaav O

Instruction: Work in groups of two or three. DUE DATE: uesaav. Overview critical a library of parameterized datapath components and use synthesis results from that library path to path for various circuits specified using a behavioral netlist. Finally, compare the timated critical actual critical path by implement the circuits using Verilog and and synthesizing the circuit. Part 1: Verilog implementation of Datapath component Library ate parameterized verilog implementations of the following datapath components Each component should be modeled using a single Verilog module. number bits fo Each module should include a Verilog meter named that specifies the of the data inputs and outputs. The following provides an overview of the required components for all students Description inputs Inputs outputs outputs Clk, Rst Register ADD a, b diff Subtractor COMP a, b gt, lt, eq Determines if a b, a b. and a b MUx2x1 a, b sel Multiplexor sh amt. Logically shifts input sh amt positions to the sh amt Logically shifts input sh amt positions to the left

Solution

Abstract— This paper presents a novel approach to verify Single-Event-Upset (SEU) protection based on smart behavioral simulation. Our analysis does not require a testbench and can perform full, exhaustive coverage within less than an hour for typical designs. Index Terms— Triplication verification, SEU Analysis, Behavioral simulation, netlist conversion, Graph Representation,