Write the VHDL code for a 24 Decoder with an Enable input Yo

Write the VHDL code for a 2-4 Decoder with an Enable input. You refer to the VHDL_note.ppt for more help.

Solution

Code can be written according to the programmer in many ways basing on logic and explained keenly below.
Code 1:

module decoder (w,En,y) //declaring inputs
   Input [1:0] w;
Input En;
   Output reg [0:3] y;
always @ (w,En) // loop starts here
   Case ({w,En})
   3\'b100:y = 4\'b1000; // Input from ports 1 & 2 processed into 3 and output port 4
3\'b101:y = 4\'b0100;
3\'b110:y = 4\'b0010;
3\'b111:y = 4\'b0001;
   default:y = 4\'b0000;
   endcase
endmodule

Or Way 2 using the ppt code just change logic :

BEGIN
Enw <= En & w;
WITH Enw SELECT
   y <= \"1000\" WHEN \"100\",
   \"0100\" WHEN \"101\",
\"0010 WHEN \"110\",
\"0001\" WHEN \"111\",
\"0000\" WHEN OTHERS;

END Behaviour