Consider a more general version of the task presented Assume

Consider a more general version of the task presented. Assume that there are four n-bit registers connected to a bus in a processor. The contents of register R are placed on the bus by asserting the control signal R_out. The data on the bus are loaded into register R on the active edge of the clock signal if the control signal R_in is asserted. Assume that three of the registers, called R1, R2, and R3, are used as normal registers. The fourth register, called TEMP, is used for temporary storage in special cases. We want to realize an operation SWAP Ri, Rj, which swaps the contents of registers Ri and Rj. This is accomplished by the following sequence of steps (each performed in one clock cycle) TEMP rightarrow [Rj] Rj rightarrow [Ri] Ri rightarrow [TEMP] Two input signals, w_1and w_2, are used to indicate that two registers have to be swapped as follows If w_2w_1 = 01, then swap R1 and R2. If w_2w_1 = 10, then swap R1 and R3. If w_2w_1 = 11, then swap R2 and R3. An input valuation that specifies a swap is present for three clock cycles. Design a circuit that generates the required control signals: R1_out, R1_in, R2_in, R3_out, R3_in, TEMP_out, and TEMP_in. Derive the next-state and output expressions for this circuit, trying to minimize the cost.

Solution

01

Temp=R2

R2=R1

R1=Temp

10

Temp=R3

R3=R1

R1=Temp

11

Temp=R3

R3=R2

R2=Temp

for data transfer from bus to register and data from external source to bus to multiplexer circuits