Design a buffer to rapidly drive a capacitive load of 1000 f

Design a buffer to rapidly drive a capacitive load of 1000 fF. Assume that the signal source is a unit inverter with Cin of 0.666fF. Determine the number of inverters in the buffer, and how many times bigger than a unit inverter each inverter is. It does not matter whether the buffer is inverting or non-inverting.

Solution

A)et us assume that we have given the output to one large inverter. Now the signal that has to drive the o/p cap will now see a larger gate capacitance of the large inverter. This results in slow rise or fall times. A unit inverter can drive approximately an inverter that 4 times bigger in size. So we need to drive a cap of 64 unit inverter then we try to keep the sizing like say 1,4,16,64. So that each inverter sees a same ratio of o/p to i/p cap. This is the main reason behind going for progressive sizing......

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Driving a very large inverter from the output of a normal (tiny) logic gate means that a large capacitance will be charged and discharged with tiny transistors. This takes a very long time, causes slow rise/fall transitions on the output pin, and causes considerable power waste in the large inverter.

Depending on the exact process parameters, it usually turns out that the lowest total propagation delay results from having a sequence of inverters. As the signal progresses from the internal logic signal to the output pin the transistors in the inverters get larger, increasing by a factor of 3X to 5X in each successive inverter.

The propagation delay is usually defined at the 50% level, but sometimes the propagation delay can be defined at other voltage levels. Also defined in this figure is the rise and fall times, tr and tf, respectively. The rise and fall times are usually measured between the 10% and 90% levels, or between the 20% and 80% levels.

The propagation delay of the inverter under different conditions can be thoroughly analyzed using circuit simulations. However, before we do that we should develop simple models suitable for hand calculations using paper and pencil to develop our basic understanding of the switching behavior. Therefore, in this section we will discuss analytical models that can be used for predicting the propagation delay through hand calculations or timing estimation tools. Also, without approximate models for back-of-the-envelope calculations we are unlikely to catch inevitable bugs in our simulation model. Through simple analytical models the good engineer develops their physical intuition to rapidly predict

The non-zero propagation delay is due to the capacitive load at the output node and the limited current driving capability of the logic gate. To calculate the propagation delay we must solve a differential equation describing the output voltage as a function of time. The solution of the differential equation is called the transient response, and the delay can be found as the time when the output reaches VDD/2.

To get any further we must have a picture of the CMOS inverter and its electrical model during the part of the charging and discharging of the load capacitor that is relevant for the propagation delay estimation.