This problem concerns the design of a circuit to find the sq

This problem concerns the design of a circuit to find the square of a floating-point number, F X 2^E. F is a normalized 5-bit fraction, and e is a 5-bit integer; negative numbers are represented in 2\'s complement. the result should be properly normalized. Take advantage of the fact that (-F)2 = F2. Draw a block diagram of the circuit. (Use only one adder and one complementer.) State your procedure, taking all special cases into account. Illustrate your procedure for^ Draw an SM chart for the main controller. You may assume that multiplication is carried out using a separate control circuit, which outputs Mdone = 1 when multiplication is complete, Write a VHDL description of the system.

Solution

--libraries to be used are specified here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--entity declaration with port definitions
entity syn_count4 is
port ( clk:     in std_logic;
   reset:   in std_logic;
   counter : out std_logic_vector(3 downto 0)
);
end syn_count4;

--architecture of entity
architecture Behavioral of syn_count4 is
--signal declaration.
signal J3,J4,Q1,Q2,Q3,Q4,Qbar1,Qbar2,Qbar3,Qbar4 : std_logic :=\'0\';

begin
J3 <= Q1 and Q2;
J4<= J3 and Q3;
--entity instantiations
FF1 : entity work.JK_Flipflop port map (clk,\'1\',\'1\',Q1,Qbar1,reset);
FF2 : entity work.JK_Flipflop port map (clk,Q1,Q1,Q2,Qbar2,reset);
FF3 : entity work.JK_Flipflop port map (clk,J3,J3,Q3,Qbar3,reset);
FF4 : entity work.JK_Flipflop port map (clk,J4,J4,Q4,Qbar4,reset);
counter <= Q4 & Q3 & Q2 & Q1;

end Behavioral;