Design a selectable 4bit updown asynchronous ripple counter

Design a selectable 4-bit up/down asynchronous ripple counter by using JK_FF and Mux2to1 in VHDL

I have done it half way but the Mode does not work. Can you spot the errors?

Here is my code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UpDownCounter is
Port ( CLOCK : in STD_LOGIC;
Reset : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (3 downto 0);
Mode : in STD_LOGIC);
end UpDownCounter;

architecture Behavioral of UpDownCounter is
component JKFlipFlop
Port ( Clock : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
reset : in STD_LOGIC;
           preset : in STD_LOGIC;
           Q : inout STD_LOGIC
           );      
end component;
component Mux2to1 is
Port ( w0 : in STD_LOGIC;
w1 : in STD_LOGIC;
s : in STD_LOGIC;
f : out STD_LOGIC);
end component;

signal ClockPulse : STD_LOGIC_VECTOR (3 downto 0);
signal Qbar: STD_LOGIC_VECTOR (3 downto 0);
signal Qtmp: STD_LOGIC_VECTOR (3 downto 0);
begin
FF1 : JKFlipFlop port map (CLOCK,\'1\',\'1\',Reset,\'1\',Qtmp(0));
Mux1: Mux2to1 port map (Qtmp(0),Qbar(0),Mode,ClockPulse(0));

FF2 : JKFlipFlop port map (ClockPulse(0),\'1\',\'1\',Reset,\'1\',Qtmp(1));
Mux2: Mux2to1 port map (Qtmp(1),Qbar(1),Mode,ClockPulse(1));

FF3 : JKFlipFlop port map (ClockPulse(1),\'1\',\'1\',Reset,\'1\',Qtmp(2));
Mux3: Mux2to1 port map (Qtmp(2),Qbar(2),Mode,ClockPulse(2));

FF4 : JKFlipFlop port map (ClockPulse(2),\'1\',\'1\',Reset,\'1\',Qtmp(3));
Mux4: Mux2to1 port map (Qtmp(3),Qbar(3),Mode,ClockPulse(3));
Qbar(0)<= Not Qtmp(0);
Qbar(1)<= Not Qtmp(1);
Qbar(2)<= Not Qtmp(2);
Qbar(3)<= Not Qtmp(3);
Q(0)<= ClockPulse(0);
Q(1)<= ClockPulse(1);
Q(2)<= ClockPulse(2);
Q(3)<= ClockPulse(3);
end Behavioral;

Solution

Here the following code shows the corrected code.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity UpDownCounter is
Port ( CLOCK : in STD_LOGIC;
Reset : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (3 downto 0);
Mode : in STD_LOGIC);
end UpDownCounter;
architecture Behavioral of UpDownCounter is
component JKFlipFlop
Port ( Clock : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
reset : in STD_LOGIC;
preset : in STD_LOGIC;
Q : inout STD_LOGIC
);
end component;
component Mux2to1 is
Port ( w0 : in STD_LOGIC;
w1 : in STD_LOGIC;
s : in STD_LOGIC;
f : out STD_LOGIC);
end component;
signal ClockPulse : STD_LOGIC_VECTOR (3 downto 0);
signal Qbar: STD_LOGIC_VECTOR (3 downto 0);
signal Qtmp: STD_LOGIC_VECTOR (3 downto 0);
begin
FF1 : JKFlipFlop port map (CLOCK,\'1\',\'1\',Reset,\'1\',Qtmp(0));
Qbar(0)<= not(Qtmp(0));
Mux1: Mux2to1 port map (Qtmp(0),Qbar(0),Mode,ClockPulse(0));
Q(0)<= ClockPulse(0);

FF2 : JKFlipFlop port map (ClockPulse(0),\'1\',\'1\',Reset,\'1\',Qtmp(1));
Qbar(1)<= not(Qtmp(1));
Mux2: Mux2to1 port map (Qtmp(1),Qbar(1),Mode,ClockPulse(1));
Q(1)<= ClockPulse(1);

FF3 : JKFlipFlop port map (ClockPulse(1),\'1\',\'1\',Reset,\'1\',Qtmp(2));
Qbar(2)<= not(Qtmp(2));
Mux3: Mux2to1 port map (Qtmp(2),Qbar(2),Mode,ClockPulse(2));
Q(2)<= ClockPulse(2);

FF4 : JKFlipFlop port map (ClockPulse(2),\'1\',\'1\',Reset,\'1\',Qtmp(3));
Qbar(3)<= not(Qtmp(3));
Mux4: Mux2to1 port map (Qtmp(3),Qbar(3),Mode,ClockPulse(3));
Q(3)<= ClockPulse(3);

end Behavioral;