Homework SourseFig 424 in the text book shows the complete singlecycle data
(Fig 4.24 in the text book) shows the complete singlecycle
datapath, which also supports the j instruction. Consider implementing the MIPS jr (jump return) instruction
(see p. 149 in MIPS Architecture Vol II-A for the encoding). Changes would have to be made to the datapath, the
control unit, both, or neither to implement jr.
(c) Kevin R. Burger :: Computer Science & Engineering :: Arizona State University Page 1
CSE/EEE 230 Computer Organization and Assembly Language Homework 6 :: 50 pts
Using any graphical drawing program you want, modify this diagram (download the PNG image from the course
website) by drawing the changes to the datapath that would need to be made to implement the jr instruction. This
may involve adding/deleting/modifying datapath components and adding/deleting/modifying control signals. Draw
your changes in red so the TA or grader can easily see your modifications.
Solution
A)Using any graphical drawing program you want, modify this diagram (download the PNG image from the course
website) by drawing the changes to the datapath that would need to be made to implement the jr instruction. This may involve adding/deleting/modifying datapath components and adding/deleting/modifying control signals. Draw your changes in red so the TA or grader can easily see your modifications.
A common manufacturing defect which can occur in the early stages of the development of a new proces
-
sor is a
stuck at 1
or
stuck at 0
defect. A stuck at 1 defect means a bit, which should be able to be set (to 1) or
cleared (to 0) is stuck at 1, i.e., it always remains set. I will let you figure out what a stuck at 0 defect is. Suppose we
are manufacturing a MIPS32 processor and two defects occur causing the
RegDst
control signal to be stuck at 1 and
the
MemToReg
control signal to be stuck at 0. Suppose we do not know that yet, but we discover that the exe
cution of the instruction which is encoded as 0x8D79_9C00 causes something to happen other than what we expected.
(a)What MIPS assembly language in struction is this? Write any numbers in decimal.
(b)Explain in English what the instruction should do, assuming no defects.
(c)Explain what the result of executing this instruction actually will do, with the defects.
Processor (CPU) is the active part of the computer, which does all the work of data manipulation and decision making.
Datapath is the hardware that performs all the required operations, for example, ALU, registers, and internal buses.
Control is the hardware that tells the datapath what to do, in terms of switching, operation selection, data movement between ALU components, etc.
In MIPS, the ISA determines many aspects of the processor implementation. For example, implementational strategies and goals affect clock rate and CPI. These implementational constraints cause parameters of the components in Figure 4.3 to be modified throughout the design process.
Such implementational concerns are reflected in the use of logic elements and clocking strategies. For example, with combinational elements such as adders, multiplexers, or shifters, outputs depend only on current inputs. However, sequential elements such as memory and registers contain state information, and their output thus depends on their inputs (data values and clock) as well as on the stored state. The clock determines the order of events within a gate, and defines when signals can be converted to data to be read or written to processor components (e.g., registers or memory). For purposes of review, the following diagram of clocking is presented:
Here, a signal that is held at logic high value is said to be asserted. In Section 1, we discussed how edge-triggered clocking can support a precise state transition on the active clock pulse edge (either the rising or falling edge, depending on what the designer selects). We also reviewed the SR Latch based on nor logic, and showed how this could be converted to a clocked SR latch. From this, a clocked D Latch and the D flip-flop were derived. In particular, the D flip-flop has a falling-edge trigger, and its output is initially deasserted (i.e., the logic low value is present).
The register file (RF) is a hardware device that has two read ports and one write port (corresponding to the two inputs and one output of the ALU). The RF and the ALU together comprise the two elements required to compute MIPS R-format ALU instructions. The RF is comprised of a set of registers that can be read or written by supplying a register number to be accessed, as well (in the case of write operations) as a write authorization bit. A block diagram of the RF
Since reading of a register-stored value does not change the state of the register, no \"safety mechanism\" is needed to prevent inadvertent overwriting of stored data, and we need only supply the register number to obtain the data stored in that register. (This data is available at the Read Data output in Figure 4.4a.) However, when writing to a register, we need (1) a register number, (2) an authorization bit, for safety (because the previous contents of the register selected for writing are overwritten by the write operation), and (3) a clock pulse that controls writing of data into the register.
In this discussion and throughout this section, we will assume that the register file is structured as shown in Figure 4.4a. We further assume that each register is constructed from a linear array of D flip-flops, where each flip-flop has a clock (C) and data (D) input. The read ports can be implemented using two multiplexers, each having log2N control lines, where N is the number of bits in each register of the RF. In Figure 4.4b, note that data from all N = 32 registers flows out to the output muxes, and the data stream from the register to be read is selected using the mux\'s five control lines. Similar to the ALU design presented in Section 3, parallelism is exploited for speed and simplicity.
In Figure 4.4c is shown an implementation of the RF write port. Here, the write enable signal is a clock pulse that activates the edge-triggered D flip-flops which comprise each register (shown as a rectangle with clock (C) and data (D) inputs). The register number is input to an N-to-2N decoder, and acts as the control signal to switch the data stream input into the Register Data input. The actual data switching is done by and-ing the data stream with the decoder output: only the and gate that has a unitary (one-valued) decoder output will pass the data into the selected register (because 1 and x = x).
