First do a dc biasing analysis and then an ac amplification

First do a dc (biasing) analysis and then an ac (amplification) analysis of the following cascaded CE setup. Assume beta 50 for both transistors for dc and ac conditions. Redraw the 2 stages for the ac case before starting your analysis, and then redraw with each NPN transistor stage replaced with the r_c model. You may assume that the influence of r_0 is negligible. Roughly what is the maximum input signal voltage that can be applied without clipping/distortion? How much biasing power is drawn from the 10-V supply?

dc analysis

Vb=Vcc*Rb2/Rb1+Rb2=3.33V

Vb=Vbe+IeRe;ie=0.55mA (Vbe=0.7v)

ic=beta*ib=27.95uA

Vc1=Vb2=0.72

ie2=-57.48mA

ic=28.74uA

ac analysis

fin=1/2pi(rs+rin)cin=23.94KHz

fout1=16.93Hz

First do a dc (biasing) analysis and then an ac (amplification) analysis of the following cascaded CE setup. Assume beta 50 for both transistors for dc and ac

First do a dc biasing analysis and then an ac amplification

Solution

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