Write a behavioral VHDL code module for a 6bit updown counte

Write a behavioral VHDL code module for a 6-bit up-down counter. If U = 1, and D = 0, the counter will count up, and if U=0, and D=1, the counter will count down. If U = D = 0, or U = D = 1, the counter will hold its state. The counter should also have an asynchronous active-low preset signal PreN that sets all flip-flips to 1. Please type or write neatly.

Test and provide code for these test cases.

- preset - set U = 0 0 0 1 1 1 - set D = 1 1 1 0 0 0

Solution

library ieee;
        
                  use ieee.std_logic_1164.all;
        
                  use ieee.std_logic_unsigned.all;
        
           entity counter is  
        
           port(C, PreN, U, D : in std_logic;
        
                   Q : out std_logic_vector(5 downto 0));
        
                         end counter;
        
            architecture archi of counter is
        
           signal tmp: std_logic_vector(5 downto 0);  
        
           begin     
        
           process (C, PreN)   
           begin       
           if (PreN=\'0\') then         
           tmp <= \"111111\";        
elsif (C\'event and C=\'1\') then
   if (U=\'1\' && D=\'0\') then  
   tmp <= tmp + 1;   
           else if (U=\'0\' && D=\'1\') then   
tmp <= tmp - 1;

           end if;        
           end if;  
           end process;   
        
             Q <= tmp;
        
           end archi;
        
           end process;
        
                 Q <= tmp;
        
           end archi;
        
              end process;
        
                 Q <= tmp;
        
           end archi;