Please read the following IEEE Spectrum articles and answer

Please read the following IEEE Spectrum articles and answer the questions given. You may want to use illustrations in your answer to the questions, and mark them up accordingly as part of answering the questions. If you take illustrations from some source (including the IEEE Spectrum articles) please make sure this is properly cited. http://spectrum.ieee.org/semiconductors/nanotechnology/the-next-highperformance-transistor-could-be-made-from-lateral-nanowires Describe a FINFET and how it works. How is it different than the planar MOSFET described in the first 5 slides of the TFET lecture? Is the FINFET a quantum device? Give reasons why or why not. How is the nanowire device described here different than the FINFET? Why is this difference an advantage for the nanowire device? They one problem with the nanowire device is capacitive coupling. What is this and explain why it is a problem with the nanowire device?

Solution

1)

The FinFET technology promises to provide the deliver superior levels of scalability needed to ensure that the current progress with increased levels of integration within integrated circuits can be maintained.

The FinFET offers many advantages in terms of IC processing that mean that it has been adopted as a major way forwards for incorporation within IC technology.

FinFET technology has been born as a result of the relentless increase in the levels of integration. The basic tenet of Moore\'s law has held true for many years from the earliest years of integrated circuit technology. Essentially it states that the number of transistors on a given area of silicon doubles every two years.

Some of the landmark chips of the relatively early integrated circuit era had a low transistor count even though they were advanced for the time. The 6800 microprocessor for example had just 5000 transistors. Todays have many orders of magnitude more.

basically what is finfet??

FinFET technology takes its name from the fact that the FET structure used looks like a set of fins when viewed.

The main characteristic of the FinFET is that it has a conducting channel wrapped by a thin silicon \"fin\" from which it gains its name. The thickness of the fin determines the effective channel length of the device.

In terms of its structure, it typically has a vertical fin on a substrate which runs between a larger drain and source area. This protrudes vertically above the substrate as a fin.

The gate orientation is at right angles to the vertical fin. And to traverse from one side of the fin to the other it wraps over the fin, enabling it to interface with three side of the fin or channel.

This form of gate structure provides improved electrical control over the channel conduction and it helps reduce leakage current levels and overcomes some other short-channel effects..

The term FinFET is used somewhat generically. Sometimes it is used to describe any fin-based, multigate transistor architecture regardless of number of gates.

Due to the increased emphasis on energy conservation and lower voltage requirements, devices that have the potential to achieve subthreshold swing (SS) steeper than the 60 mV/dec thermionic limit have become attractive. Tunneling Field Effect Transistors (TFETs) utilize a gate modulated tunnel barrier to control the I-V characteristics and allow the device to circumvent the thermionic limit [1]. One drawback of TFETs is that tunneling through such a barrier can severely limit the drive current of the device. To mitigate this limitation, III-V material systems, with their direct bandgaps and wide variety of band alignments, have been proposed. While recently there have been reports of III-V TFETs with higher drive current than their group IV counterparts [2] [3] [4], all these devices exhibit inferior SS compared to thin body III-V MOS high electron mobility transistors (HEMT). This work demonstrates the steepest SS (<60mV/dec) ever reported in a III-V TFET, and for the first time, is significantly steeper than the best thin body III-V MOS HEMT in literature [5]

2)

Nanowires Applications in Energy

Researchers at MIT have developed a solar cell using graphene coated with zinc oxide nanowires. The researchers believe that this method will allow the production of low cost flexible solar cells at high enough efficiency to be competive.

Sensors powered by electricity generated by piezoelectric zinc oxide nanowires. This could allow small, self contained, sensors powered by mechanical energy such as tides or wind

Researchers are using a method called Aerotaxy to grow semiconducting nanowires on gold nanoparticles. They plan to use self assembly techniques to align the nanowires on a substrate; forming a solar cell or other electrical devices. The gold nanoparticles replace the silicon substrate on which conventional semiconductor based solar cells are built.

Researchers at the Nies Bohr Institute have determined that sunlight can be concentrated in nanowires due to a resonance effect. This effect can result in more efficient solar cells, allowing more of the energy from the sun to be converted to electricity.

Using light absorbing nanowires embedded in a flexible polymer film is another method being developed to produce low cost flexible solar panels.\'

Using electrodes made from nanowires that would enable flat panel displays to be flexible as well as thinner than current flat panel displays.

Using nanowires to build transistors without p-n junctions.

Using nanowires made of an alloy of iron and nickel to create dense memory devices. By applying a current magnetized sections along the length of the wire. As the magnetized sections move along the wire, the data is read by a stationary sensor. This method is called race track memory.

Using silver nanowires embedded in a polymer to make conductive layers that can flex, without damaging the conductor.

Sensors using zinc oxide nano-wire detection elements capable of detecting a range of chemical vapors.

these are some applications of nanowire which differentiate it from mosfets.

3)Capacitive coupling is the transfer of energy within an electrical network or between distant networks by means of displacement current between circuit(s) nodes, induced by the electric field. This coupling can have an intentioIn its simplest implementation, capacitive coupling is achieved by placing a capacitor between two nodes.In its general form the coupling is described by a capacitance matrix C_ij. Where C_ii are self-capacitance coefficients and C_ij ij are mutual capacitance coefficients

We have modeled the field and space charge distributions in back-gate and top-gate nanowire field effect transistors by solving the threedimensional Poisson’s equation numerically. It is found that the geometry of the gate oxide, the semiconductivity of the nanowire, and the
finite length of the device profoundly affect both the total amount and the spatial distribution of induced charges in the nanowire, in stark
contrast to the commonly accepted picture where metallic dielectric properties and infinite length are assumed for the nanowire and the
specific geometry of the gate oxide is neglected. We provide a comprehensive set of numerical correction factors to the analytical capacitance
formulas, as well as to numerical calculations that neglect the semiconductivity and finite length of the nanowire, that are frequently used for
quantifying carrier transport in nanowire field effect transistors.

C=qVgate [Nd - n(V) + p(V)] dx dy dz