A Verilog implementation of a Dflipflop with reset is given

A Verilog implementation of a D-flipflop with reset is given below. Find two problems in this code and explain why with waveform. module dff (q, ck, d, rb); input ck, d, rb; output q; always @ (posedge ck or rb) begin if (rb == 1\'b0) q

Solution

module dff(
input ck,d,rb,
output q
);
always @(posedge ck or rb)
begin
if(rb==1\'b0) q<=1\'b0;//Procedural assignment to a non-register q is not permitted, left-hand side should be reg
else if (rb==1\'b1) q<=d;//Procedural assignment to a non-register q is not permitted, left-hand side should be reg
else q<=1\'bx;//Procedural assignment to a non-register q is not permitted, left-hand side should be reg
end

endmodule

The error line is q<=d,q<=1\'b0;q<=1\'bx; its Procedural assignment to a non-register q is not permitted, left-hand side should be reg.

we can declare the q is as register to correct this error

erreor free code:

module dff(
input ck,d,rb,
output reg q
);
always @(posedge ck or rb)
begin
if(rb==1\'b0) q<=1\'b0;
else if (rb==1\'b1) q<=d;
else q<=1\'bx;
end

endmodule