httpsmybbqueduqabboswebdavpid297127dtannouncementrid2639339

https://mybb.qu.edu.qa/bboswebdav/pid-297127-dt-announcement-rid-2639339 2/courses/ College of Engineering QATAR UNIVERSITY Department of Electrical Engineering Digital Systems Design (ELEC261) Exercise Write the VHDL code for circuit A using xOR gate and circuit A as components. entity for XOR gate Circuit A 2 entity xor gate is port( 10, 11: in std logic; O: out std logic end xor gate; A(1) B1) A(0) B(0) entity for circuit B gate entity circuit B is port( b0, b1, b2: in std logic 00, 01 out st logic B Hot B end circuit B; Y (1)

Solution

main circuit A:

entity A is
Port ( A,B : in STD_LOGIC_VECTOR (1 downto 0);
   X: in STD_LOGIC;
C : out STD_LOGIC_VECTOR (1 downto 0);
          
Y : out STD_LOGIC);
end A;

architecture Behavioral of A is
component XOR_GATE is
Port ( I0,I1 : in STD_LOGIC;
O : out STD_LOGIC);
END COMPONENT;
component circuit_B is
Port ( b0,b1,b2 : in STD_LOGIC;
O0,O1 : out STD_LOGIC);
END COMPONENT;
signal i,j,k,m,n:std_logic;
begin

u1:XOR_GATE port map(X,\'1\',i);
u2:XOR_GATE port map(X,B(0),j);
u3:XOR_GATE port map(X,B(1),k);
u4:circuit_B port map(A(0),j,i,C(0),m);
u4:circuit_B port map(A(1),k,i,C(1),n);
u5:XOR_GATE port map(X,n,Y);

end Behavioral;

sub ckt b:

entity circuit_B is
Port ( b0,b1,b2 : in STD_LOGIC;
O0,O1 : out STD_LOGIC);
end circuit_B;

architecture Behavioral of circuit_B is

begin
O0<=(b0 xor b1) xor b2;
O1<=(b0 and b1)or(b0 and b2) or (b1 and b2);

end Behavioral;

for xor:

entity XOR_gate is
Port ( I0,I1 : in STD_LOGIC;
O : out STD_LOGIC);
end XOR_gate;

architecture Behavioral of XOR_gate is

begin

O<=I0 xor I1;
end Behavioral;