Consider a 32bit byte addressable direct mapped cache storin

Consider a 32-bit, byte addressable, direct mapped cache storing only 16 bytes with a block size of 4 bytes and where an integer is 4 bytes. If the cache starts empty and elements of an array of integers are accessed in this order: array[0], array[4], array[4], array[0] The first access to Array [0] is The second access to array [0] The first access to array [4] is a The second access to array [4] is a

Solution

Answer with explanation:

The first access to array[0] is cold miss. Because it is the first reference to array[0] and the cache is empty.
The second access to array[0] is hit. Because it is already in cache.
The first access to array[4] is capcity miss. Because the cache is not big enough to hold both array[0] and array[4].
The second access to array[4] is hit. Because it is already in cache.