In this assignment you will continue the Flight Search Engin

In this assignment you will continue the Flight Search Engine mini-project by creating additional classes, and practicing logic in arrays. The classes you create must be compatible with either the classes you submitted last week, or our posted solution. Please indicate which in a comment at the top of the classes. Included for you are two simple testing classes that you can use to verify the top-level functionality of your system. Do not submit them.

Q1: [FlightSearchEngine Mini-Project] Create an Itinerary class. This class will represent a travel itinerary containing one or two flights in our system. It should contain two constructors, two instance variables (two different Flights) and seven methods (getFirstFlight, getSecondFlight, hasConnection, getTotalCost, getDeparture, getArrival, toString) [15 points]

overloaded constructor: will take one Flight object and use it to set up the instance variables. The second Flight variable should be set to null.

overloaded constructor: will take two Flight objects and use them to set up the instance variables.

getFirstFlight(): returns the first Flight in the itinerary.

getSecondFlight(): returns the second Flight in the itinerary.

hasConnection(): returns true if the itinerary contains two Flight objects.

getTotalCost(): returns the total cost of all Flights in the itinerary.

getDeparture(): returns the departure time of the first flight in the itinerary.

getArrival(): returns the arrival time of the last flight in the itinerary.

toString(): will return the total cost of the itinerary and the \"detailed string\" for the Flight or Flights in the itinerary.

Sample Output from ItineraryTest.:

Q2: [FlightSearchEngine Mini-Project] Create a FlightManager class. This class will store instances of the Flight class, and support generating a list of potential itineraries. It should contain one constructor, two instance variables (an array of Flights, and something that counts the number of flights in the system), and four methods (addFlight, increaseSize, findItineraries, shrinkItineraries). [25 points]

default constructor: will set up the instances variables with zero flights.

addFlight(...): Adds a flight to the flights array. Uses the increaseSize() method if the array is full.

increaseSize(): Doubles the size of the flights array, while keeping whatever is already there. Make this a private method.

findItineraries(...): Searches the flights based on source airport, destination airport, and departure time, to find 1-flight and 2-flight itineraries meeting those criteria. When searching for 2-flight itineraries, checks that the flights have a connecting city, and that the first arrives in time for the second. Your method should create an array of potential itineraries that can be returned.  (If it helps, you may assume that this method will never find more than 100 itineraries.) Use the shrinkItineraries() method to \"clean up\" up the potential itineraries array; see below. Hint: use loops to search for all the flights in the flights variable, check if they meet the criteria, and then create a new Itinerary object if the criteria is met.

shrinkItineraries(...). Takes an array of itineraries, where some of the later indices are unused (null), and returns a new array of itineraries where there are no empty indices. Make this a private method.

Sample Output from FlightManagerTest:

Solution

The successive approximation analog-to-digital converter circuit normally includes 4 chief subcircuits:

A sample and preserve circuit to collect the input voltage (Vin).
An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the end result of the comparison to the successive approximation sign up (SAR).
A successive approximation check in subcircuit designed to deliver an approximate virtual code of Vin to the internal DAC.
An inner reference DAC that, for contrast with VREF, supplies the comparator with an analog voltage equal to the digital code output of the SARin.
The successive approximation check in is initialized so that the most tremendous bit (MSB) is same to a digital 1. This code is fed into the DAC, which then substances the analog equal of this digital code (Vref/2) into the comparator circuit for comparison with the sampled enter voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1. Then the subsequent bit is ready to at least one and the same take a look at is done, persevering with this binary search until each bit within the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is sooner or later output by means of the SAR at the give up of the conversion (EOC).

Mathematically, let Vin = xVref, so x in [1, 1] is the normalized enter voltage. The goal is to about digitize x to an accuracy of one/2n. The set of rules proceeds as follows:

preliminary approximation x0 = 0.
ith approximation xi = xi1 s(xi1 x)/2i.

in which, s(x) is the signum-feature (sgn(x)) (+1 for x zero, 1 for x < zero). It follows the use ofxn xshown within the above set of rules, a SAR ADC calls for:

An input voltage source Vin.
A reference voltage source Vref to normalize the enter.
A DAC to transform the ith approximation xi to a voltage.
A comparator to perform the feature s(xi x) by means of evaluating the DAC\'s voltage with the enter voltage.
A sign up to save the output of the comparator and follow xi1 s(xi1 x)/2i.
successive approximation
ADC the usage of successive approximation
instance: the 10 steps to converting an analog input to 10 bit virtual, the use of successive approximation, is shown here, for all voltages from 5V to 0V in 0.1V iterations. for the reason that reference voltage is 5V, whilst the enter voltage is also 5V all bits are set. because the voltage is reduced to 4.9V, just a few of the least considerable bits are cleared. The MSB will stay set until the input is one 1/2 the reference voltage, 2.5V.

The binary weights assigned to each bit, beginning with the MSB, are 2.five, 1.25, 0.625, zero.3125, 0.15625, zero.078125, 0.0390625, zero.01953125, 0.009765625, zero.0048828125. All of those add as much as four.9951171875, that means binary 1111111111, and is one LSB much less than 5.

when the analog input is being as compared to the internal DAC output, it successfully is being as compared to each of those binary weights, beginning with the two.5V and either maintaining it or clearing it as a result. Then with the aid of adding the subsequent weight to the preceding end result, comparing once more, and repeating until all of the bits and their weights were in comparison to the enter, the give up end result, a binary variety, representing the analog enter, is determined.

price-redistribution successive approximation ADC[edit]

fee-scaling DAC
one of the maximum common implementations of the successive approximation ADC, the fee-redistribution successive approximation ADC, makes use of a price scaling DAC. The fee scaling DAC surely includes an array of personally switched binary-weighted capacitors. the amount of fee upon each capacitor within the array is used to perform the aforementioned binary seek at the side of a comparator inner to the DAC and the successive approximation sign in.

First, the capacitor array is absolutely discharged to the offset voltage of the comparator, VOS. This step presents automated offset cancellation(i.e. The offset voltage represents not anything however dead rate which can not be juggled by means of the capacitors).
next, all the capacitors inside the array are switched to the enter signal, vIN. The capacitors now have a fee identical to their respective capacitance times the enter voltage minus the offset voltage upon each of them.
inside the 0.33 step, the capacitors are then switched so that this fee is applied throughout the comparator\'s input, creating a comparator input voltage identical to vIN.
in the end, the actual conversion system proceeds. First, the MSB capacitor is switched to VREF, which corresponds to the entire-scale variety of the ADC. due to the binary-weighting of the array the MSB capacitor forms a 1:1 fee divider with the rest of the array. thus, the input voltage to the comparator is now vIN plus VREF/2. eventually, if vIN is greater than VREF/2 then the comparator outputs a digital 1 because the MSB, otherwise it outputs a digital 0 because the MSB. each capacitor is tested within the equal way until the comparator enter voltage converges to the offset voltage, or at least as near as feasible given the decision of the DAC.

three bits simulation of a capacitive ADC
Use with non-best analog circuits[edit]
when carried out as an analog circuit – wherein the price of each successive bit isn\'t always flawlessly 2N (e.g. 1.1, 2.12, four.05, eight.01, and so forth.) – a successive approximation approach might not output the suitable value due to the fact the binary seek set of rules incorrectly removes what it believes to be half of the values the unknown input can\'t be. depending at the difference between actual and ideal overall performance, the most errors can without difficulty exceed numerous LSBs, especially as the error among the actual and perfect 2N becomes big for one or extra bits. considering the fact that we do not know the actual unknown input, it is consequently very critical that accuracy of the analog circuit used to put into effect a SAR ADC be very near the precise 2N values; otherwise, we can\'t guarantee a first-class in shape search.