Can someone please provide the VHDL code for this encoder Th

Can someone please provide the VHDL code for this encoder? Thank you!

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder_case is
    port(
        din : in STD_LOGIC_VECTOR(9 downto 0);
        dout : out STD_LOGIC_VECTOR(4 downto 0)
         );
end encoder_case;


architecture encoder_case_arc of encoder_case is
begin

    encoder : process (din) is
    begin
        case din is
            when \"1000\" => dout <= \"00\";
            when \"0100\" => dout <= \"01\";
            when \"0010\" => dout <= \"10\";
            when \"0001\" => dout <= \"11\";
            when others => dout <= \"ZZ\";
        end case;
    end process encoder;

end encoder_case_arc;