Using Verilog and schematic symbols implement and test a cir

Solution

If you can express working of a digital circuit and visualize the flow of data inside a IC, then learning any HDL or Hardware Description Language is very easy. This chapter is a overview of how Verilog code looks like.

This article will always be under construction.

Let us start with an AND gate. Here is the truth table:

Now let us try to understand the code.

/* This is multi line
comment */
and           // this is single line comment, Comments are same as in C language.

In verilog, one circuit is represented by set of \"modules\". We can consider a module as a black box. With this assumption, if you draw a block diagram of the circuit with a set of signals connection each other, that is called top level design. Then go on writing modules for each black box, then design that black box with in the same way. This is how we are designing a circuit. You will understand this concept after studying some examples. A module may be one gate, one flip-flop, one register, one ALU one controller or one SOC. Go back to the example. Here, module is keyword, andgate is the name given to the module in this examples and a, b and y are the ports or connections to the module. Every modules and with the keyword endmodule.

In the beginning of a module, we have to declare all ports as input output or inout. By default, ports will have one pin or one bit.

Using \'assign\' statement, we connected inputs and outputs via AND gate. A will be ANDed with B and will be connected to Y. Here, we are not going to store the values, and hence we did not declare any registers. By default, all the ports will be considered as wires. If we want the output to be latched, we have to declare it using the keyword \'reg\'.

input a, b;
output y;
wire a, b, y;

Now let us try to understand the code.

/* This is multi line
comment */
and           // this is single line comment, Comments are same as in C language.

In verilog, one circuit is represented by set of \"modules\". We can consider a module as a black box. With this assumption, if you draw a block diagram of the circuit with a set of signals connection each other, that is called top level design. Then go on writing modules for each black box, then design that black box with in the same way. This is how we are designing a circuit. You will understand this concept after studying some examples. A module may be one gate, one flip-flop, one register, one ALU one controller or one SOC. Go back to the example. Here, module is keyword, andgate is the name given to the module in this examples and a, b and y are the ports or connections to the module. Every modules and with the keyword endmodule.

In the beginning of a module, we have to declare all ports as input output or inout. By default, ports will have one pin or one bit.

Using \'assign\' statement, we connected inputs and outputs via AND gate. A will be ANDed with B and will be connected to Y. Here, we are not going to store the values, and hence we did not declare any registers. By default, all the ports will be considered as wires. If we want the output to be latched, we have to declare it using the keyword \'reg\'.

input a, b;
output y;
wire a, b, y;

  /* A simple AND gate   File: and.v              */  

  module andgate (a, b, y);  input a, b;  output y;  

  assign y = a & b;  

  endmodule