Write the behavioral verilog for addersubstractor given 4 bi

Write the behavioral verilog for adder/substractor: given 4- bit inputs A and B, and 1-bit input M as control bit. For M = 0, the output is given by S (S4 S3 S2 S1 S0 ) = A (A3 A2 A1 A0 ) + B (B3 B2 B1 B0) (Addition), while when M = 1 yields SUM = A + 2\'s complement of B = A - B (Subtraction). (Strongly suggest you use the conditional operator (?:), or ‘if then else’ statements combined with the arithmetic method for summing two vectors, i.e. Sum=A+B;. In other words, use the M bit to steer yourself around.)

Solution

module add_sub(
input [3:0] A,
input [3:0] B,
input M,
output reg [4:0] S
);
reg C[4:0];
reg D[3:0];
always@(A,B,M)
begin
D=B^(4\'b1111);
C={0,D}+5\'b00001;
if(M=0)
S={0,A}+{0,B};
else
S={0,A}+{0,C[3:0]};
end
endmodule