In the circuit below the delay from clock to Q is 2 ns and t

In the circuit below, the delay from clock to Q is 2 ns and the delay from Q of FF1 to D of FF2 is 4 ns. The two clock signals Clk1 and Clk2 may have a skew of 2 ns. Which of the setup time and hold time can the circuit satisfy (The clock skew has to be due to wire length, so you could just say that clock 2 is 2ns later than clock 1 because of wire delay) Clock frequency = 100MHz, Tsetup = 3ns, Thold = 3ns Clock frequency = 80MHz, Tsetup = 2ns, Thold = 5ns Clock frequency = 66MHz, Tsetup = 5ns, Thold = 3ns Clock frequency = 80 MHz, Tsetup = 3ns, Thold = 5ns

Solution

Tclkq+Tcl_pdmin = Tskew + Thold

Thold = Tclkq+Tcl_pdmin+Tqd-Tskew

where Tclkq = Time required from clock to Q=2ns
   Td = 2ns

Thold = (2+1+4-2)ns = 5ns

TW= maxTpff+tsu-min tinv

Tsetup=tsu=2ns
Clock frequency = 80Mhz
Option b