2 Using the ifhenelse statement complete the VHDL code for a

2. Using the if..hen...else statement, complete the VHDL code for a 1-to-4 Demultiplexer shown below, where input X and outputs a, b, c, d are all 4-bit vectors 2 -a DEMUX ENTITY port IS END ; ARCHITECTURE OF IS process( if then then elsif then else end process END

Solution

2.
entity demultiplexer1_4 is
port(
X : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
a : out STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC_VECTOR (3 downto 0);
d : out STD_LOGIC_VECTOR (3 downto 0);

);
end demultiplexer1_4;

architecture demultiplexer1_4_arc of demultiplexer1_4 is
begin

demux : process (din,sel) is
begin
if (sel=\"00\") then
a <= X;
elsif (sel=\"01\") then
b <= X;
elsif (sel=\"10\") then
c <= X;
else
d <= X;
end if;
end process demux;

end demultiplexer1_4_arc;

3.
entity demultiplexer1_4 is
port(
X : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR(1 downto 0);
a : out STD_LOGIC_VECTOR (3 downto 0);
b : out STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC_VECTOR (3 downto 0);
d : out STD_LOGIC_VECTOR (3 downto 0);
);
end demultiplexer1_4;

architecture demultiplexer_case_arc of demultiplexer1_4 is
begin

demux : process (X,sel) is
begin
case sel is
when \"00\" => a <= X;
when \"01\" => b <= X;
when \"10\" => c <= X;
when others => d <= X;
end case;
end process demux;

end demultiplexer_case_arc;

5.
entity counter is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
   UP_DOWN: in STD_LOGIC;
Q :buffer unsigned (3 downto 0)
);
end counter;

architecture behavorial of counter is
Begin
   Process(reset,clk,UP_DOWN)

begin
if (reset=\'1\') then
Q := 0;
elsif (rising_edge (clk)) then
   if(UP_DOWN=\"1\")
m := m + 1;
   else
    m:= m -1;
end if;
   end if;
end process;
end behavorial;