VLSI DESIGN OBJECTIVE QUESTIONS Unit1 1 Which of the materia

VLSI DESIGN OBJECTIVE QUESTIONS
Unit-1
1. Which of the material used as gate [ ]
a). photoresistive b). polysilicon c). metal d). glass

2. The ---------- of the VLSI chip ranges from pre-assembly wafer preparation to fabrication techniques for the packages that provide electrical connections and mechanical and environmental
protection [ ]
a). placement b). Floorplanning c). Packaging d). None

3. ------------------ is the electrical consideration for VLSI packages [ ]
a) low ground resistance . b) short signal leads c) minimum power supply spiking d) All

4. A MOS transistor which has conducting channel region at zero gate bias is called [ ]
a) Depletion mode b) Enhancement mode c) Saturated mode d) Non- saturated mode

5. If packing density area and performance are the constraints, power dissipation is not a constraint, the
technology you prefer [ ]
a).BJT b) CMOS c). NMOS d). PMOS

6. The speed of the CMOS logic is less, when compared to other technologies due to [ ]
a) High noise immunity b) High input capacitance c) High driven current d) All

7. A sink current is obtained under which condition. [ ]
a.)Logic high input b) Logic low input c) Logic high output d) Logic low output

8. Which logic family has highest speed of operation [ ]
a) TTL b) DTL c) ECL d) All the above

9. The partial current flowing through p and n channels is called [ ]

a) Voltage spikes b) current spikes c) both a and b d) none of the above

10. -------------- is the non-saturated digital logic family [ ]
a) TTL b) ECL c) MOS d) RTL
11. Which logic family has very good noise immunity? [ ]
a) RTC b) DTL c) TTL d) ECL

Solution

1.poly silicon (b)

2.placement(a)

3.All (d)

4.Depletion mode(a)

5.BJT(a)

6. All (d)

7.Logic low output(d)

8.TTL(a)

9.Current spike (b)

10.ECL(b)

11.TTL(c)