Write a Verilog model for the following state diagram using

Write a Verilog model for the following state diagram using 3 always block Is this is Mealy machine or Moore? eset S1 SO LA: green LA: yellow L.: red red LS: red La: red L.: red L. red LA La yellow La: red LB: red green

Solution

its moore type machine since the output changes depends only state of the machine.

Verilog Code:

`timescale 1ns/1ns

module trafficlight (
clock,reset,TA,
LARED,LAGreen,LAYellow,LBRed,LBGreen,LBYellow);

input clock;
input reset;
input TA;
tri0 reset;
tri0 TA;
output LARED;
output LAGreen;
output LAYellow;
output LBRed;
output LBGreen;
output LBYellow;
reg LARED;
reg reg_LARED;
reg LAGreen;
reg reg_LAGreen;
reg LAYellow;
reg reg_LAYellow;
reg LBRed;
reg reg_LBRed;
reg LBGreen;
reg reg_LBGreen;
reg LBYellow;
reg reg_LBYellow;
reg [5:0] fstate;
reg [5:0] reg_fstate;
parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5;

initial
begin
reg_LARED <= 1\'b0;
reg_LAGreen <= 1\'b0;
reg_LAYellow <= 1\'b0;
reg_LBRed <= 1\'b0;
reg_LBGreen <= 1\'b0;
reg_LBYellow <= 1\'b0;
end

always @(posedge clock)
begin
if (clock) begin
fstate <= reg_fstate;
end
end

always @(fstate or reset or TA or reg_LARED or reg_LAGreen or reg_LAYellow or reg_LBRed or reg_LBGreen or reg_LBYellow)
begin
if (reset) begin
reg_fstate <= S0;
reg_LARED <= 1\'b0;
reg_LAGreen <= 1\'b0;
reg_LAYellow <= 1\'b0;
reg_LBRed <= 1\'b0;
reg_LBGreen <= 1\'b0;
reg_LBYellow <= 1\'b0;
LARED <= 1\'b0;
LAGreen <= 1\'b0;
LAYellow <= 1\'b0;
LBRed <= 1\'b0;
LBGreen <= 1\'b0;
LBYellow <= 1\'b0;
end
else begin
reg_LARED <= 1\'b0;
reg_LAGreen <= 1\'b0;
reg_LAYellow <= 1\'b0;
reg_LBRed <= 1\'b0;
reg_LBGreen <= 1\'b0;
reg_LBYellow <= 1\'b0;
LARED <= 1\'b0;
LAGreen <= 1\'b0;
LAYellow <= 1\'b0;
LBRed <= 1\'b0;
LBGreen <= 1\'b0;
LBYellow <= 1\'b0;
case (fstate)
S0: begin
if (TA)
reg_fstate <= S0;
else if (~(TA))
reg_fstate <= S1;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= S0;

reg_LAGreen <= 1\'b1;

reg_LAYellow <= 1\'b0;
reg_LAYellow <= 1\'b0;

reg_LBGreen <= 1\'b0;

reg_LARED <= 1\'b0;

reg_LBRed <= 1\'b1;
end
S1: begin
reg_fstate <= S2;

reg_LAGreen <= 1\'b0;

reg_LAYellow <= 1\'b1;

reg_LBYellow <= 1\'b0;

reg_LBGreen <= 1\'b0;

reg_LARED <= 1\'b0;

reg_LBRed <= 1\'b1;
end
S2: begin
reg_fstate <= S3;

reg_LAGreen <= 1\'b0;

reg_LAYellow <= 1\'b0;

reg_LBYellow <= 1\'b0;

reg_LBGreen <= 1\'b0;

reg_LARED <= 1\'b1;

reg_LBRed <= 1\'b1;
end
S3: begin
if (TA)
reg_fstate <= S3;
else if (~(TA))
reg_fstate <= S4;
// Inserting \'else\' block to prevent latch inference
else
reg_fstate <= S3;

reg_LAGreen <= 1\'b0;

reg_LAYellow <= 1\'b0;

reg_LBYellow <= 1\'b0;

reg_LBGreen <= 1\'b1;

reg_LARED <= 1\'b1;

reg_LBRed <= 1\'b0;
end
S4: begin
reg_fstate <= S5;

reg_LAGreen <= 1\'b0;

reg_LAYellow <= 1\'b0;

reg_LBYellow <= 1\'b1;

reg_LBGreen <= 1\'b0;

reg_LARED <= 1\'b1;

reg_LBRed <= 1\'b0;
end
S5: begin
reg_fstate <= S0;

reg_LAGreen <= 1\'b0;

reg_LAYellow <= 1\'b0;

reg_LBYellow <= 1\'b0;

reg_LBGreen <= 1\'b0;

reg_LARED <= 1\'b1;

reg_LBRed <= 1\'b1;
end
default: begin
reg_LARED <= 1\'bx;
reg_LAGreen <= 1\'bx;
reg_LAYellow <= 1\'bx;
reg_LBRed <= 1\'bx;
reg_LBGreen <= 1\'bx;
reg_LBYellow <= 1\'bx;
$display (\"Reach undefined state\");
end
endcase
LARED <= reg_LARED;
LAGreen <= reg_LAGreen;
LAYellow <= reg_LAYellow;
LBRed <= reg_LBRed;
LBGreen <= reg_LBGreen;
LBYellow <= reg_LBYellow;
end
end
endmodule // trafficlight