Write EntityArchetcture for 3 bit twisted ring counter with

Solution

find the VHDL code as below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity twisted_ring_counter is
Port ( clk : in STD_LOGIC;
inp : in STD_LOGIC_VECTOR (2 downto 0);
load : in STD_LOGIC;
rst : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (2 downto 0));
end twisted_ring_counter;
architecture arch of twisted_ring_counter is
signal tmp : STD_LOGIC_VECTOR(2 downto 0);
begin
process(clk)
begin
  
if( clk\'event and clk=\'1\' ) then
  
if (rst = \'1\') then
tmp <= \"000\";
  
elsif ((rst = \'0\') and (load = \'1\')) then
tmp <= inp;
  
elsif ((rst = \'0\') and (load = \'0\')) then
  
tmp(1) <= tmp(0);
tmp(2) <= tmp(1);
tmp(0) <= not (tmp(2));

end if;
  
end if;
  
end process;
output<=tmp;
end arch;

it is a rising edge counter with synchronous active high reset

clk,rst ,load and inp is the input the counter.

at the rising edge of the clock

if rst is high than output is zero.

if rst is 0 means low and load is 1 output is equal to input that is parallel load

if rst is 0 means low and load is 0 counter starts counting