A MIPSbased computer system with 2 GB of main memory that is

A MIPS-based computer system with 2 GB of main memory that is built on a single circuit board. It is designed with a single control signal between the CPU chip and main memory, i.e. one bit of control that is set to one for Read operations and zero for Write operations.

a) How many bits wide is the main memory data bus?

b) How many bits wide is the main memory address bus when 4-banks memory interleaved is used?

c) How long does it takes to fetch 8 words from the memory to MIPS registers? Assume that one cycle is required to place the address and one cycle to transfer one word.

d) Find the memory bandwidth and compare it to memory bandwidth when no memory interleaved is used.

Solution

Is assumed to be a system or RISC machine which has as its word width of 32 bits buses this for the case of bus width for directions or records. In this case the memory is 2Gb therefore 2 ^ 32 bytes have.

In the case of these data buses they have the same length of 32 bits because it is sending a word.

if interspersed bank records used at the same time then the width of the buses could increase up to the amount of bank records obtained.

The format for these instructions corresponds to:
op rs rt rd shamt funct
6 bits 5bits 5bits 5bits 5bits 6bits
op: instruction operation. It indicates the type of operation that is ..
rs: first record of the source operand.
rt: second source operand register.
rd: register destination operand; You obtain the result of the operation.
shamt: amount of displacement
funct: function; This field selects the variant of the operation of the field op.
The problem occurs when an instruction that needs major fields
shown above (for example, a load instruction should be specified
two registers and an address, so the address would be reduced to 32 positions
by heart). This is too small to be a useful direction for data.
Therefore, we have a conflict between the desire that all instructions have
the same length and the desire that the instructions have a simple format.
It will be necessary to establish a second type of instruction format.
2.2 Instruction Type I
Such instructions are critical because this is the
instructions for loading data-storage, and the ALU can only
operate with the data once they have been loaded into the records. This leads to
those records loaded into memory locations with which we want to operate.
The format for data transfer instructions corresponds to the
shown below.
op rs rt address
6 bits 5bits 5bits 16bit

The word width of the data buses depend on the instruction to apply more however should not exceed 32 bits

this takes 16 cycles because each memory sending the registration is done one at a time and therefore while the instruction is obtained and stored in memory should be expected given the corresponding machine cycle. Also if the width of the instruction word is greater than the width of the bus another cycle more could be expected. But in this particular case 16 cycles is expected to send each instruction from memory to record.

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