i have wrote a 4bit regester shift vhdl code and having prob

i have wrote a 4bit regester shift vhdl code and having problems with the test bench.

here is the code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity R4BitShift is
port(sel,serialIn,clk: in std_logic;
D: in std_logic_vector(3 downto 0);
   Q: out std_logic_vector(3 downto 0));
end R4BitShift;

architecture Behavioral of R4BitShift is

signal Qint: std_logic_vector(3 downto 0);

begin
process(clk)
begin
   if(clk\'event) and (clk = \'1\') then
       if sel = \'0\' then
       Qint(3) <= D(3);
       Qint(2) <= D(2);
       Qint(1) <= D(1);
       Qint(0) <= D(0);
       else
       Qint(3) <= Qint(2);
       Qint(2) <= Qint(1);
       Qint(1) <= Qint(0);
       Qint(0) <= serialIn;
       end if;
   end if;
end process;
Q <= Qint;
end Behavioral;

i have wrote this test bench but it is wrong. Can anyone fix it please

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY R4bit_tb IS
END R4bit_tb;

ARCHITECTURE behavior OF R4bit_tb is

COMPONENT R4BitShift

PORT(sel,serialIn,clk: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0));
END COMPONENT;

--Inputs
signal sel : std_logic := \'0\';
signal clk : std_logic := \'0\';
signal serialIn : std_logic := \'0\';
signal D: std_logic_vector(3 downto 0):= (others => \'0\');

--Outputs
signal Q : std_logic_vector(3 downto 0);

constant Clk_in_period : time := 10 ns;
BEGIN

uut: R4BitShift PORT MAP (
sel => sel,
clk => clk,
serialIn => serialIn,
Q => Q,
D=>D
);

clk_process :process

begin
clk <= \'0\';
wait for Clk_in_period/2;
clk <= \'1\';
wait for Clk_in_period/2;
end process;

stim_proc: process

begin
wait for 10ns;
serialIn <= \'1\';
sel<=\'1\';
wait for 200ns;
serialIn <= \'0\';
wait;
end process;

begin
wait for 10ns;
Q <= \'1\';
D<=\'1\';
wait for 200ns;
Q <= \'0\';
end process;

please fix the test bench

Solution

Testbench Code:

library ieee;
use ieee.std_logic_1164.all;

ENTITY _tb is
END register_tb;

architecture behavior of R4BIT_tb is

component R4BITSHIFT
port(
Din : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR(3 downto 0) );
end component;

signal Din : STD_LOGIC;
signal CLK : STD_LOGIC;
signal RST : STD_LOGIC;

signal Qout : STD_LOGIC_VECTOR(3 downto 0);

begin

UUT : register_design
port map (
   Din => Din,
   CLK => CLK,
   RST => RST,
   Qout => Qout
);

CLK_GEN: process
begin
CLK <= \'0\';
wait for 5 ns;

CLK <= \'1\';
wait for 5 ns;

end process;

stimuli : process
begin

Din <= \'1\' after 20 ns;

Din <= \'1\' after 90 ns;

wait;

end process
end TESTBENCH_FOR_register_design;