What value would you store in the mode register of the SDRAM

What value would you store in the mode register of the SDRAM we had in class in you wanted a full burst capability (for both read and write operations) and a CAS latency of 2?

Solution

READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. When a burst is finished, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated.

Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus

NOTE

NOTE

M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).

M8, M7: Operating mode. Reserved, and must be 00.
M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.
M3: Burst type. 0 - requests sequential burst ordering, while 1 requests interleaved burst ordering.
M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type