You are to design a circuit and model using HDL that 1 adds

You are to design a circuit, and model using HDL, that 1) adds two three bit unsigned binary numbers, 2) includes a flag to determine when a overflow occurs, and 3) includes a flag indicating whether the resulting sum is even or odd, for example if the sum is 3, it is odd. You should create a test bench and test your design by completing the sums below. 000 + 000 010 + 011 111 + 001 Your inputs and outputs should be defined as follows: A[2:0] B[2:0] Represent your binary inputs, 0 defines least significant bit Sum Represents the output sum Represents the overflow flag, no overflow = 0 P Represents the even/odd flag, even = 0

Solution

here its very simple to create the test bench by xilinx software

so please use of it to get the test bench program HERE I CREATED MY TEST BENCH FOR MORE DIGITS THAN YOU ASK BY SEEING IT YOU CAN REDUCE AS PER YOUR REQUIRMENT....

module binary_to_bcd;

reg clk_i, ce_i, rst_i, start_i, dat_binary_i;

wire dat_bcd_o, done_o;

initial begin
clk_i=0; ce_i=0; rst_i=0; start_i=0; dat_binary_i=
16\'b0000000000000000;

end
always begin
#5 rst_i=1;
#5 rst_i=0;
#5 ce_i=1;
#5 start_i=1;
#5 dat_binary_i=16\'b0000000000000101;
#20 dat_binary_i=16\'b0001010000100101;
#20 dat_binary_i=16\'b0101100100000011;
#20 dat_binary_i=16\'b1000011000100101;
#20 dat_binary_i=16\'b1001000010010101;
#20 dat_binary_i=16\'b1001001001010101;
end
initial
#130 $finish;

always begin
#1 clk_i=!clk_i;
end
endmodule