The beginning of a particular communications system is denoted by the occurrence of \"y\" consecutive high levels (1\'s) on a line called \"DATA\". Data on this line has already been synchronized with a source of checks pulse. Design a clocked sequential \"Message Detector\" circuit which will produce a DATARDY signal of \"1\" only at the clock time coinciding with the third of a sequence of three 1\'s on the \"DATA\" line. The circuit will serve to warm the receiving system of the beginning of an incoming serial message. It will be provided with a separate reset circuit, that you are not responsible, for. to place it in state so following the end of a message but you should show this on your state Transition Diagram. To help you understand the above specifications is \"basic\" block diagram and typical timing diagram are shown below. Neatly show all \"9\" steps presented in the lecture on sequential logic design? Realize the circuit for the \"Message Detector\" using all 3-K-Flip-Flopes so A can see it!
OK when we observe the circuit assume message detector as the jk flip flop as you need and jk flip flop outputs are q and q bar( if q=1 then q bar becomes 0) by observing the above circuit of basic block diagram data may be 0 or 1 depends upon data signal and the same signal is given to digital system and clock signal is given to message detector as it is countinous signal and depends upon the clock the message signal gives output of data is ready and further the signal is sends to digital system for further process
And by observing the timing diagram the clock signal and it is countinously equal at any time interval
And data signal is a signal that has a particular data which we need I.e information is send through this data signal
And data ready is a signal that indicates the data is ready to transmit or ready to receive