Use the following SRC code fragment and make the pipeline ex

Use the following SRC code fragment and make the pipeline execution explained in Fig. 5.6. Fill out the values of the pipeline registers in the first clock cycle (C1) to the fifth clock cycle (C5).

           

200:      shr       r1, r3, 2            ; R[3] = 32

204:      sub       r2, r5, r1           ; R[5] = 8, R[1] = 1

208:      brlnv    r4                     ;

212:      ld         …                    ;

            …….

C1

Stage 1

IR2

PC

PC2

C2

Stage 1

IR2

PC

PC2

Stage 2

IR3

X3

Y3

MD3

PC

C3

Stage 1

IR2

PC

PC2

Stage 2

IR3

X3

Y3

MD3

PC

Stage 3

IR4

Z4

MD4

C4

Stage 1

IR2

PC

PC2

Stage 2

IR3

X3

Y3

MD3

Cond

PC

Stage 3

IR4

Z4

MD4

Stage 4

IR5

Z5

C5

Stage 1

IR2

PC

PC2

Stage 2

IR3

X3

Y3

MD3

Cond

PC

Stage 3

IR4

Z4

MD4

Stage 4

IR5

Z5

Stage 5

Stage 1	IR2	PC	PC2

Solution

C1:

C2:

C3:

C4:

C5:

Stage	IR2	PC	PC2
	shr r1,r2,2	200	204