4 a i Write the VHDL code entity and architecture to impleme

4) (a) (i) Write the VHDL code (entity and architecture) to implement the 1-bit half adder shown in Fig. 4

(ii) Write the VHDL code (entity and architecture) to implement the 1-bit full adder shown in Fig. 4(a)(ii).

(c) The logic diagram of a ripple carry adder is shown in Fig. 4(a)(i). It consists of one 1-bit half adder and three 1-bit full adders (Fig. 4(a)(ii)). A, B and D are 4-bit numbers. Use the 1-bit half adder and 1-bit full adder as components to write the VHDL code (entity and architecture) to implement the ripple carry adder using the appropriate design approach.

B(0) HA D(0) A(0) Half Sum Adder C1 Cout 12 (HA) B(1) FA. D(1) um F 12 A(1) Cout I1.12 C2 B(2) D(2) FA. H Full Suma A(2) 12 Adder Cout (FA) Cin C3 B(3) Sum I1 12 Cin FA. D(3) A(3) Cout 3I1. 12+ (I1 12). Cin C4 (ii) Fig. 4(a) (i) Ripple carry adder (ii) 1-bit half adder and 1-bit full adder

Solution

c)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ripple_carry_adder is
Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
C4 : in STD_LOGIC);
end ripple_carry_adder;

architecture Behavioral of ripple_carry_adder is
component HA
Port ( I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
sum,cout : out STD_LOGIC);
end component;
component FA
Port ( I1,I2,Cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
signal c1,c2,c3:STD_LOGIC;
begin

HA1: HA port map(A(0), B(0), D(0),c1);
FA1: FA port map(A(1),B(1),c1,D(1),c2);
FA2: FA port map(A(2),B(2),c2,D(2),c3);
FA3: FA port map(A(3),B(3),c3,D(3),C4);

end Behavioral;

b)

entity FA is
Port ( I1,I2,Cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end FA;

architecture Behavioral of FA is
component HA
Port ( I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
sum,cout : out STD_LOGIC);
end component;
signal x,y,z:STD_LOGIC;
begin

G1: HA port map(A, B, x,y);
G2: HA port map(x, Cin, sum,z);
cout<=y or z;
end Behavioral;

a)

entity HA is
Port ( I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
sum,cout : out STD_LOGIC);
end HA;

architecture Behavioral of HA is

begin
sum<=I1 xor I2;
cout<=I1 and I2;

end Behavioral;