In VHDL what are the allowed outputs for a BIT signal type 0

In VHDL, what are the allowed outputs for a BIT signal type?

0, 1

True, false

0, 1, Z

-231 to (231 – 1)

Write the VHDL text file for an adder to handle three 5-bit input values (A, B, and C). Use INTEGER types and ignore overflows. (Points : 10)

Solution

Answer for allowed outputs for a BIT signal type is

Clock to Output Delay

0, 1, Z

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VHDL text file:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab8_final is
Port ( x : in std_logic_vector(4 downto 0);
y : in std_logic_vector(4 downto 0);
s0 : out std_logic_vector(4 downto 0));
end lab8_final;

architecture Behavioral of lab8_final is
signal c : std_logic_vector (4 downto 0):=\"0000\";
component lab8ex3
port(a,b,cin:in std_logic;
s,cout:out std_logic);
end component;

begin

bit1: lab8ex3 port map (a=>x(0), b=>y(0), s=>s0(0), cin=>c(0), cout=>c(1));
bit2: lab8ex3 port map (a=>x(1), b=>y(1), s=>s0(1), cin=>c(1), cout=>c(2));
bit3: lab8ex3 port map (a=>x(2), b=>y(2), s=>s0(2), cin=>c(2), cout=>c(3));
bit4: lab8ex3 port map (a=>x(3), b=>y(3), s=>s0(3), cin=>c(3), cout=>c(0));
bit5: lab8ex3 port map (a=>x(4), b=>y(4), s=>s0(4), cin=>c(4), cout=>c(4));

end Behavioral;