3 TCOs 1 and 4 A VHDL design file includes the following sta

3. (TCOs 1 and 4) A VHDL design file includes the following statement: IF (CLOCK’EVENT and CLOCK = 1) THEN. Which signal type in the signal CLOCK? (Points : 6)       

BIT
BOOLEAN
INTEGER
STD_LOGIC

Solution

If(clk\'event and clk=\'1\' ) then the result will be TRUE when the present value is \'1\' . There is an edge transition in the clk and does not see whether the previous value is \'0\' or not. So this signal is bit as well as boolean.