3 Write the verilog implementation of a half adder using beh

Write the verilog implementation of a half adder using behavioral, procedural data flow modelling:

Solution

half-adder code using behavioral modelling :

entity HA is

port(

A,B:in STD_LOGIC:

S,CY: out STD_LOGIV

):

end HA

architecture HA_arch of HA is

begin

S<=A XOR B:

CY<=A AND B:

end HA-arch

half-adder code using data flow modelling :

library ieee:

use iee.std_logic_1164 all:

entity half_adder is

port (a,b:in bits,c:output):

end half_adder

archittecture half_adder of half adder is

begin

s<=(a xor b):

c<=(a and b):

end half-adder: