Computer Systems question provide the full MARIE RTN registe

Computer Systems question.

provide the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction).

Question: 3) AddJump X – fetch the datum at location X and add it to the PC.

Solution

Recall that there are 15 MARIE instructions. With the 4-bit op code, we can add one additional instruction. For questions 2-4, provide the full MARIE RTN (register transfer notation) for the described operation. Your answer should include the fetch, decode, operand fetch (if necessary), execution and store result (if necessary) stages. When you see X in these instructions, this is a main memory address (the last 12 bits of the 16-bit instruction). 2) Inc X – fetch datum at location X, increment it and store it back to location X. 3) AddJump X – fetch the datum at location X and add it to the PC. 4) ResetOnPos X – if the AC is currently storing a positive number, change the value stored at memory location X to 0. For 5-6, convert the C code to equivalent MARIE code. Assume that a numeric value is stored in a variable of that name (e.g., one stores 1, two stores 2, etc), or use #number for a numeric value in an instruction, as in Add #1 (to add 1 to the AC) or Load #5 to put 5 in the AC. 5) if(x >= y && y > z) x++; else y++; 6) sum = 0; for(i=0;i0) sum+=num; else sum--; } printf(“%d”, sum); 7) Instead of one data register, the AC, we want to provide MARIE with two registers which we will call AC0 and AC1 and we denote the register by using a bit in the instruction after the op code, as in op code – register bit – operand. The operand is used the same as before but now for instructions like Add, Load, we can use either register. Making this change will impact other aspects of the computer. Describe why and what impacts this will have. 8) Assume a CPU has the following instruction format: op code num operands [mode1 operand1] [mode2 operand2] Instructions will have 1 or 2 operands, each of which will have its own mode specifier and the instruction will include a bit to indicate 1 operand or 2. The CPU’s instruction set has 191 operations (op codes) and there are 7 different addressing modes available. Assume a fixed length 32-bit instruction. Answer the following and offer a brief explanation for each answer. a. One type of instruction will use two registers for the operands. How many registers at most should we provide? b. Assuming we have 64 registers, if an instruction has a register and an immediate datum as its two operands, how large can the immediate datum be assuming it is represented in 2’s complement? c. One mode is base displacement which specifies both a register and an offset. Assume that if this mode is used for one operand, the other operand must be a register. If this machine has 32 registers, what is the largest displacement possible? Assume displacements are in unsigned magnitude. d. One mode is a direct memory address. Assume this mode can only be used if there are no other operands. What is the largest memory address that can be referenced? 9) Assume the following values are in memory, and register R1 is the index register and is storing 5000. What is loaded into the accumulator with the instruction “Load 3000” given each of the following addressing modes? Address Data 3000 7000 a. Immediate … … b. Direct 5000 2000 c. Indirect … … d. Indexed 7000 8000 … … 8000 3000 … … 10) Two computers have 12-stage fetch-execute cycles where branches are determined in stage 5. One computer is not pipelined, and the other is pipelined. Assuming that tp = 1, answer the following questions when running a program with 5,000 instructions where 250 of the instructions are branches and each branch skips over 8 instructions. a. How much faster is the pipelined machine over the non-pipelined machine assuming that no branches are taken. b. How much faster is the pipelined machine over the non-pipelined machine assuming that all branches are taken. c. Bonus question: How many branches would the program have to have assuming every branch is taken (and every branch skips over 8 instructions) for the non-pipelined machine to execute the program at the same speed as the pipelined machine?