Give VHDL code that represents the multiplier circuit below

Give VHDL code that represents the multiplier circuit below (DO NOT USE PROCESS)

Solution

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
port( n1, n2: in std_logic_vector(1 downto 0);
product: out std_logic_vector(3 downto 0));
end multiplier;

begin
process(n1, n2)

var n1_reg: std_logic_vector(2 downto 0);
var product_reg: std_logic_vector(5 downto 0);

begin

n1_reg := \'0\' & n1;
product_reg := \"0000\" & n2;
for i in 1 to 3 loop
if product_reg(0)=\'1\' then
product_reg(5 downto 3) := product_reg(5 downto 3)+ num1_reg(2 downto 0);
end if;
product_reg(5 downto 0) := \'0\' & product_reg(5 downto 1);
end loop;
product <= product_reg[3 downto 0);

end process;

end behv;