Write down the forwarding logic in pseudocode form for cases

Write down the forwarding logic in pseudo-code form for cases as follows where the destination register an R-type instruction happens to be the source register of an immediately next instruction: add $t5, $t0, $tl sub $t6, $t5, $t3 Note: Please take care of the situation where the destination register could be the $zero register. Implement the forwarding logic in c) to generate MUX control signal using logic gates.

Solution

Often a compiler can reorder the obvious sequence to provide a sequence
that is less likely to stall.

Consider the code sequence:          A = B + E;
                                                        C = B + F;

A straightforward compilation would yield something like the follow, which is
written in pseudo–MIPS assembly language.

    LW    $T1, B           #$T1 GETS VALUE OF B

    LW    $T2, E           #T2 GETS VALUS OF E

    ADD   $T3, $T1, $T2    #DATA HAZARD.ON $T2

    SW    $T3, A

    LW    $T4, F

    ADD   $T5, $T1, $T4    #ANOTHER DATA HAZARD

    SW    $T5, C

Using a Clever Compiler (Part 2)

Again, here is the code sequence:  A = B + E;
                                                        C = B + F;

A good compiler can emit a non–obvious, but correct, code sequence,
such as the following.  This allows the pipeline to move without stalls.

    LW    $T1, B         # $T1 GETS A

    LW    $T2, E         # $T2 GETS E

    LW    $T4, F         # AVOID THE BUBBLE

    ADD   $T3, $T1, $T2  # $T1 AND $T2 ARE BOTH READY

    SW    $T3, A         # NOW $T4 IS READY

    ADD   $T5, $T1, $T4

    SW    $T5, C

Note that the reordered instruction sequence has the correct semantics; the effect of
each instruction sequence is the same as that of the other.

Moving the Load F instruction up has two effects.

    1.   It provides “padding” to allow the value of E to be available when needed.

    2.   It places two instructions between the load of F and the time the value is used.