Preferably using Cadence to build the schematic and a mobili

Preferably using Cadence to build the schematic and a mobility ratio of 2.

Setup the Circuit for the NAND Gate in the Schematic: The two-input CMOS NAND gate circuit is shown below. Use Wn=1.5um for NAND gate.

Solution

Given: 1. Width of NMOS transistor as 1.5um, and 2. Mobility ratio of NMOS to PMOS = 2

Required: we have to calculate the width of PMOS transistors in such a way that setup and hold times of the CMOS circuit is comparable in worst case scenario.

Note: Typically, in a CMOS transistor the gate lengths of NMOS and PMOS are same and equal to minimum gate length. Therefore, I am assuming the same for this question. Therefore, gate length is not required.

(W) total of NMOS * (Mobility) = (W) of PMOS equation 1

(Note: Since, we are required to calculate gate lengths considering the worst case scenario, we have to assume only one of the PMOS is on i.e. current is flowing through only one branch. )

Since, the NMOS are connected in series

(W/L) total of NMOS = ( W_first NMOS * W_second NMOS)/ (W_first NMOS + W_second NMOS)

= W_N²/ (2WN) = W_N/2 where W_N = 1.5um (given)

putting thisvalue in equation 1 given above

(W_N/2) * 2 = W_P or W_P = W_N = 1.5 um.

Therefore, Width of the two PMOS transitors will also be equal to 1.5um