Give the steps for selecting channel converting data and get

Give the steps for selecting channel, converting data, and getting the data out of ADC. State the role of the GO/DONE bit.

Step 1. We enable the port clock for the pin that we will be using for the ADC input.

Step 2. Make that pin an input by writing zero to the DIR register.

Step 3. Enable the alternative function on that pin by writing one to the AFSEL register.

Step 4. Disable the digital function on that pin by writing zero to the DEN register.

Step 5. Enable the analog function on that pin by writing one to the AMSEL register.

Step 6. We enable the ADC clock by setting bit 16 of the SYSCTL_RCGC0_R register.

Step 7. Bits 8 and 9 of the SYSCTL_RCGC0_R register specify the maximum sampling rate of the ADC. In this example, we will sample slower than 125 kHz, so the maximum sampling rate is set at 125 kHz. This will require less power and produce a longer sampling time, creating a more accurate conversion.

Step 8. We will set the priority of each of the four sequencers. In this case, we are using just one sequencer, so the priorities are irrelevant, except for the fact that no two sequencers should have the same priority.

Step 9. Before configuring the sequencer, we need to disable it. To disable sequencer 3, we write a 0 to bit 3 (ASEN3) in the ADC_ACTSS_R register. Disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process.

Step 10. We configure the trigger event for the sample sequencer in the ADC_EMUX_R register. For this example, we write a 0000 to bits 15–12 (EM3) specifying software start mode for sequencer 3.

Step 11. Configure the corresponding input source in the ADCSSMUXn register. In this example, we write the channel number to bits 3–0 in the ADC_SSMUX3_R register. In this example, we sample channel 9, which is PE4.

Step 12. Configure the sample control bits in the corresponding nibble in the ADC0SSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. Sequencer 3 has only one sample, so we write a 0110 to the ADC_SSCTL3_R register. Bit 3 is the TS0 bit, which we clear because we are not measuring temperature. Bit 2 is the IE0 bit, which we set because we want to the RIS bit to be set when the sample is complete. Bit 1 is the END0 bit, which is set because this is the last (and only) sample in the sequence. Bit 0 is the D0 bit, which we clear because we do not wish to use differential mode.

Step 13. We enable the sample sequencer logic by writing a 1 to the corresponding ASENn. To enable sequencer 3, we write a 1 to bit 3 (ASEN3) in the ADC_ACTSS_R register.

void ADC0_InitSWTriggerSeq3_Ch9(void){ volatile unsigned long delay;

SYSCTL_RCGC2_R |= 0x00000010; // 1) activate clock for Port E

delay = SYSCTL_RCGC2_R; // allow time for clock to stabilize

GPIO_PORTE_DIR_R &= ~0x04; // 2) make PE4 input

GPIO_PORTE_AFSEL_R |= 0x04; // 3) enable alternate function on PE2

GPIO_PORTE_DEN_R &= ~0x04; // 4) disable digital I/O on PE2

GPIO_PORTE_AMSEL_R |= 0x04; // 5) enable analog function on PE2

SYSCTL_RCGC0_R |= 0x00010000; // 6) activate ADC0

delay = SYSCTL_RCGC2_R;

SYSCTL_RCGC0_R &= ~0x00000300; // 7) configure for 125K

ADC0_SSPRI_R = 0x0123; // 8) Sequencer 3 is highest priority

ADC0_ACTSS_R &= ~0x0008; // 9) disable sample sequencer 3

ADC0_EMUX_R &= ~0xF000; // 10) seq3 is software trigger

ADC0_SSMUX3_R &= ~0x000F; // 11) clear SS3 field

ADC0_SSMUX3_R += 9; // set channel Ain9 (PE4)

ADC0_SSCTL3_R = 0x0006; // 12) no TS0 D0, yes IE0 END0

ADC0_ACTSS_R |= 0x0008; // 13) enable sample sequencer 3

GO/DONE:

A/D Conversion Status bit

If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete)

The first line checks if the input channel provided by the user is valid or not. Then we select ADC channel. After that we switch on the module by setting ADON bit. Then conversion is started by setting the GODONEbit. As soon as the GODONE bit is set to 1 the module starts the conversion process. As long as the module is busy the GODONE bit is HIGH, and when the conversion is complete it is cleared by the module. So we wait in the while loop as long as GODONE is high. Remember that the while loop is empty (a semi colon just after it), so as long as GODONE is high the CPU will do nothing. As soon as GODONE is cleared the while loop breaks and we switch of the module by writing 0 to the ADON bit. Finally the result of conversion is returned, ADRES register holds the converted value.