d flipflop synrst data in data out clock reset SolutionVHDL

d flipflop synrst data in data out clock reset

Solution

VHDL Code for D flip flop with syncronous input is give below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFF is
port(
Q : out std_logic;
CLK : in std_logic;
RESET : in std_logic;
D : in std_logic);
end DFF;

architecture Behavioral of DFF is
begin
process(CLK)
begin
if ( CLK\'event and CLK=\'1\' ) then
if (RESET = \'1\') then
Q <= \'0\';
else
Q <= D;   
end if;
end if;   
end process;
end Behavioral;