Exercise 168 Fibonacci numbers I Draw the block diagram for

Exercise 16.8 Fibonacci numbers, I. Draw the block diagram for a datapath circuit to compute 16-bit Fibonacci Numbers. During each cycle, the circuit should output the next Fibonacci number (starting with 0 after reset). The circuit should signal when the next number is larger than 16 bits. (15 points)

Do not use a lookup table to solve this problem. This is sequential logic (chapter 14), not combinational logic. That means it can remember the previous Fibonacci number and do addition.

Exercise 16.9 Fibonacci Numbers, II. Implement your datapath FSM from Exercise 16.8 in Verilog. (10 points)

Solution

`timescale 1ns / 1ps
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// Company:
// Engineer:
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// Create Date: 18:19:54 10/21/2016
// Design Name:
// Module Name: fibonacci
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fibonacci(
input rst,clk,
output reg [15:0] fibseq
);

reg [15:0] Reg1;
reg [16:0] Reg2;
//bit pattern is printed in decimal for convenience
initial
begin
$monitor($time , \" : FibSeq = %d \", fibseq);
end
always@(posedge clk or negedge rst)
begin
//on reset, initialize reg1 to 0
if(rst == 1\'b0) begin
Reg1<=16\'b0000000000000000;
Reg2<=16\'b0000000000000001;
end
else if(clk==1\'b1)
begin
//Reg1 and Reg2 will infer registers
Reg1 <= Reg2;
Reg2 <= Reg2 + Reg1;
if(Reg2[8] == 1)
$display(\"\\t\\tout of range ERROR\");
//Copy Reg1 to output
assign fibseq = Reg1;
end
end
endmodule