How could we schedule the following code to make use of a si

How could we schedule the following code to make use of a single cycle delayed branch slot?
Loop: lw $2, 100($3) /* load reg $2 with contents of memory at address 100+$3 */
addi $3, $3, 4 /* $3 ß $3 + 4 */
beq $3, $4, Loop / * branch if contents of $3 = contents $4 to label Loop */

Solution

clearly,any one of the lw or the addi must occupy the branch delay slot.The addi is cannot be just put into the slot ,why because,the branch instruction needs to compare $3 with the register $4 and the addi instructions changes $3.$3 is to be changed,inorder to move the load (lw) into the branch delay slot.

If we consider this as a two step transformation,then

Rewriting the code as follows:

Loop: addi $3, $3, 4

lw $2, 96($3)

  beq $3, $4, Loop

Now we can move the load into branch delay slot :

Loop: addi $3, $3, 4

  beq $3, $4, Loop

  lw $2, 96($3) # branch delay slot