module Verilogexample input 150 A B C D output 150 vwxyz ass

module Verilog-example( input [15:0] A, B, C, D, output [15:0] v,w,x,y,z assign v 16\'o121156; assign w assign x=A+B; assign z=-B; assign y = (A-C); endmodule // Bitwise Subtract // Bitwise Add // Bitwise Complement // Equality

Solution

v=16\'o121156; its octal number convert to binary

1-001

2-010

1-001

1-001

5-101

6-110

v=001010001001101110

convert this to hexa decimal;

v=00 1010 0010 0110 1110

V=16\'h A26E

w=C-D

C=16\'O51253...CONVER TO BINARY

C=16\'b 0101001010101011

D=16h 52AB..convert to Binary

5-0101

2-0010

A-1010

B-1011

D=16\'b 0101001010101011

w=C-D=0101 0010 1010 1011 -0101 0010 1010 1011

W=0000000000000000 convert to hex

W=16\'h 0000

x=A+B

A=16\'b 0101 0010 1010 1011

B=16\'d 21163=16\'b 0101 0010 1010 1011

X=A+B=0101 0010 1010 1011+0101 0010 1010 1011=0 1010 0101 0101 0110 conver to hexa decimal

x=16\'h A556

Y=1 if A==C, i given problem A==C, check the binary eqauallant of C its equal with A

so Y=16\'h 0001

Z=~B

B=16\'b 0101 0010 1010 1011

~B=16\'b 1010 1101 0101 0100 convert to Hexa

Z=16\'b AD54