Use Verilog HDL to design 2 to 1 MUX Using 2 to 1 MUX as a c

Use Verilog HDL to design 2 to 1 MUX. Using 2 to 1 MUX as a component, design 4 to 1, then using 4 to 1 plus other components design 8 to 1 MUX. Now use your 8 to 1 MUX component to design the following combinational logic: Z = AB + AB + AC and Z = 3 input minority detector using Verilog HDL.

Solution

(1)Verilog code for 8x1 mux using 4x1 and 2x1

Verilog code for Mux2x1:

module Mux2x1(
input sel,
input I1,I0,
output F
);
assign F = sel?I1:I0;

endmodule

Verilog code for Mux 4x1:

module Mux4x1(
input [1:0] sel,
input I3,I2,I1,I0,
output F
);
   wire lowbit,highbit;
Mux2x1 mux1(sel[0],I1,I0,lowbit);
Mux2x1 mux2(sel[0],I3,I2,highbit);
Mux2x1 mux3(sel[1],highbit,lowbit,F);

endmodule

Verilog code for mux 8x1

module Mux8x1(
input [2:0] sel,
input I7,I6,I4,I5,I3,I2,I1,I0,
output F
);
   wire lowbit;
Mux4x1 mux1(sel[1:0],I3,I2,I1,I0,lowbit);
Mux4x1 mux2(sel[1:0],I7,I6,I5,I4,highbit);
Mux2x1 mux3(sel[2],highbit,lowbit,F);

endmodule

Verilog code for function Z=AB+AB\'+A\'C:

Z=ABC+ABC\'+AB\'C+AB\'C\'+A\'BC+A\'B\'C=sum of(7,6,5,4,3,2)

module funz(
input A,B,C,
output Z
);
wire sel[2:0];
assign sel[0]=C;
assign sel[1]=B;
assign sel[2]=A;
Mux8x1 z1(A,B,C,\"1\",\"1\",\"1\",\"1\",\"1\",\"1\",\"0\",\"0\",Z);
endmodule